1. Field of the Invention
The present invention relates to a CMOS output stage, particularly adapted for use in analog circuits, audio devices, and for general application to any kind of operational amplifier.
2. Discussion of the Related Art
Analog circuits using MOS transistors suffer a drawback related to P-channel MOS transistors, whose threshold voltage drifts over time (changes value). This drift effect is caused by hot electrons trapped in the gate oxide and is particularly evident for transistors operating at high current densities and high voltages, such as power transistors used in operational amplifiers.
CMOS output stages are known wherein a MOS transistor in a diode configuration is employed as a reference for the gate voltage to be applied to the power MOS transistor when quiescent (i.e., when there is no output signal). The reference does not drift, because the current density flowing through the MOS transistor and the voltage across it are both low. However, the threshold of the power MOS transistor, which has to withstand intense currents and high voltages, drifts and thus causes undesirable variations in the quiescent current.
FIG. 1, which illustrates a conventional CMOS output stage, shows that a diode-connected MOS transistor and a reference current source are used for each power MOS transistor in order to set its quiescent current.
In particular, for the P-channel power MOS transistor 10, a diode-connected P-channel reference MOS transistor 12 is provided with a corresponding reference current source 14, and a differential stage 16 including two P-channel MOS transistors and two N-channel MOS transistors. Likewise, circuit elements that are mirror-symmetrical to those described above namely reference N-channel MOS transistor 20 and reference current source 22, are used for the N-channel power MOS transistor 18.
In the quiescent state, the voltage across the gate and source of the reference transistor 12 is reproduced across the gate and source of the power transistor 10 (the same occurs for reference transistor 20 and the power transistor 18). Therefore, in the quiescent state the current delivered by the power transistor is equal to the ratio of the channel geometries of the power transistor and of the reference transistor, multiplied by the value of the reference current set by the reference current source; assuming their threshold voltages are equal, the reference transistor and the power transistor are in a current mirror configuration.
The total quiescent current is the sum of the quiescent current conducted by the drain terminal of the P-channel power transistor 10 and of the current conducted by the N-channel power transistor 18 (which is not affected by threshold drift).
The above-described output stage suffers a first drawback: the quiescent current depends on the threshold voltage of the P-channel power transistor 10, which tends to vary over time (tends to decrease), whereas the threshold voltage of the P-type reference transistor 12 remains substantially constant over time. This decrease in the threshold voltage of the power transistor 10 results in an increase in the current delivered for the same gate voltage, which is unacceptable for some applications.
Further drawbacks include a considerable circuit area and a complicated circuit structure.